FPGA Design/Verification Engineer
Location:Denver, CO, United States (Anywhere)Education level: Some college/University
Education field: Engineering
Years of experience: more than 5
Attributes that best describes:
Strong analytical skills
Dear Potential Client,
My name is Terry Jackson Sr., I’m an FPGA Designer with seventeen plus years of programmable logic development experience. Specifically, six years of ASIC front-end verification and FPGA design and verification development for the HDC (Hard Disk Controller) and the Aerospace industry. The prior eleven plus years was committed to CPLDs/PALs/GALs logic devices where the targeted applications were directed towards the medical, printer, and robotics industry etc. In regards to Xilinx Vertex-5, 6 and Xilinx ISE tool suite, I’m familiar, to a degree, with this FPGA’s architecture and development environment for this technology. I have implemented within this device at one time or another, 32-Bit SDR SDRAM controller block, 16-Bit PWM controller block, 16-Bit QSPI controller block, RS232 Serial controller, 4-Client Round-Robin Bus Arbiter, 32-Bit ECC block, 16-BIT MAC block as well as test benches for RTL functional verification of these blocks, and many other miscellaneous RTL functions/sub-functions were also implemented. The Xilinx ISE was specifically used on my own personal project(s), and not with any professional client(s). I was able to obtain a free web version of their software that supported the Vertex-5 architecture – I think I can reload this software if necessary. All professional FPGA contracts listed on my resume were for clients utilizing Actel, Altera and Lattice technologies with Actel being the most relevant.
Terry Jackson Sr.
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